Job Listing Description

Electrical Engineer Designer

PDS Tech Inc. is seeking a ASIC Verification Eng, in Tucson, AZ.

The Verification Electrical Engineer will create the verification plan with the Program and Register-Transfer Level (RTL) designers input and review in addition to developing the architecture and design of the environment. This requires creating the necessary run and/or post-processing scripts as well as the overall methodology for the given project in terms of the logistics related to using the verification environment. You will also participate in a team of engineers to implement the test benches. The Verification Electrical Engineer will also be involved in the implementation of the verification environment which may include: Creation of Constrained Random Agents; Creation of Monitors, coverage collectors, and Scoreboards; Incorporation of available models that may exist as C/C++, Verilog or VHDL, etc., and/or creation of those models; Creation of functional coverage through use of assertions; Use of functional and code coverage as a quantitative measure to analyze and help determine what is considered 100% coverage for the given design as determined by the verification plan; Writing directed and constrained random tests in parallel with RTL designers to help achieve coverage goals; and use of trouble reports and bug tracking. 
Required Skills: U.S. Citizenship is required Experience with a scripting languages and utilities such as Make, Perl, Python, or Tcl Experience with a HDL languages such as Verilog and VHDL Experience with the HVL language System Verilog.
Job Number: 1810090103
Job Location: Tucson, AZ
Duration: 12 months
Input Date: 01/07/2019
Attention: Terry Brooke
Address: 1839 S ALMA SCHOOL RD STE 250
City, State: MESA, AZ 85210
Phone: 480/929-9922
800 Phone: 800/657-0997
Fax Phone: 480/929-9779

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