Job Listing Description

Design Engineer

Description:
PDS Tech Inc. is seeking a Design Engineer, in Redmond, WA.

Summary:
  • Implement algorithm blocks as RTL code as defined in the Micro Architecture.
  • Implement RTL using HLS and System Verilog.
  • Support DV team for verification of blocks.
  • Assist with synthesis and timing closure.
  • Work with FPGA engineers to perform early prototyping.
  • Support handoff and integration of blocks into larger SOC environments.
  • Assist with Algorithm analysis, verification and improvement.
  • Contribute to ASIC digital architecture, design and verification.
  • Ability to document and communicate clearly.


 
Prerequisites:
  • 5-8 years of experience as a Digital Design Engineer.
  • Experience with HLS Catapult tool is a big plus but not a must.
  • Experience in RTL coding, Lint/CDC tools, synthesis and LEC tools.
  • HLS coding using Catapult and Xilinx Vivado tools.
  • System Verilog OVM/UVM DV experience.
  • Python (or similar) scripting experience.
  • ASIC design experience.
  • Masters Degree in EE.
  • BS Electrical Engineering/Computer Science or equivalent experience.

 
Job Number: 1810091403
Job Location: Redmond, WA
Duration: 6 months
Input Date: 10/11/2018
Firm Name: PDS TECHNICAL SERVICES
Attention: Soluna Ortega
Address: 1839 S ALMA SCHOOL RD STE 250
City, State: MESA, AZ 85210
Phone: 480/929-9922
800 Phone: 800/657-0997
Fax Phone: 480/929-9779
Email: cecjphoenix@pdstech.com
Website: https://pdsjobs.force.com/candidates/job_detail?id=a1i50000002ezt7AAA&URLSource=cjhunter

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